알림
뒤로
알림 설정
뒤로
더보기
게시물 알림
내 글 반응
내가 작성한 게시물이나 댓글에 다른 사람이 댓글이나 답글을 작성하면 알려줍니다.
공지사항
사이트에서 보내는 중요한 공지를 실시간으로 알려줍니다.
  • Alarm
    프로필 정보수정
  • 마이페이지 로그아웃
  • Company
    • About us
    • CEO
    • Partnership
    • Contact us
  • Business
    • Semiconductor Chip Design Solution
    • Biotech
      • Drug Repositioning solution
      • AI-based Biobetter Design
      • AI-based Nanobody Design
    • Supply Chain
  • Products
    • G. O. A. L.
    • repoGItion
  • News
    • Press Release
    • Media Coverage
    • Announcement
    • Awards
  • Recruit
  • Resource
  • Company
    • About us
    • CEO
    • Partnership
    • Contact us
  • Business
    • Semiconductor Chip Design Solution
    • Biotech
      • Drug Repositioning solution
      • AI-based Biobetter Design
      • AI-based Nanobody Design
    • Supply Chain
  • Products
    • G. O. A. L.
    • repoGItion
  • News
    • Press Release
    • Media Coverage
    • Announcement
    • Awards
  • Recruit
  • Resource
MENU
Company
Business
Products
News
Recruit
Resource

Macro placement in System-on-a-Chip


 During the floor planning stage of the physical design process, the placements of macros are considered. This crucial step determines the locations and orientations of macro cells within the chip's layout. By carefully arranging the macros, designers aim to achieve desired objectives such as optimizing performance, reducing power consumption, minimizing area utilization, and ensuring efficient connectivity. The floor planning process plays a vital role in shaping the overall physical layout of the System-on-a-Chip (SoC) and sets the foundation for subsequent design stages.

Global Optimization Assisted pLacement


GOAL delivers highly optimized macro placement solutions for the SoC design, with a dual focus on reducing routing wirelength and minimizing routing congestion to enhance overall performance. Traditionally, macro placement during floorplanning has relied on the experience and knowledge of backend engineers. However, as the number of instances in SoC design grows, this manual approach became relatively time-consuming, resulting in the major factor for delay in time-to-market.


 To overcome these challenges and to expedite time-to-market, one needs an efficient macro placement solution. GOAL was developed to address a very complex combinatorial optimization problem of macro placement. By utilizing the Conformational Space Annealing (CSA) global optimization technique, GOAL explores the vast solution space of macro placement where locations as well as orientations of macro cells are variables, and generates a collection of diverse and well-optimized macro placements that satisfy various design objectives and constraints.


With GOAL, design efficiency, accuracy, and time-to-market for SoC designs can be greatly improved. This enables designers to meet project timelines while delivering high-quality products.

SNS 바로가기



  • 이용약관
  • 개인정보처리방침