Macro placement in System-on-a-Chip
During the floor planning stage of the physical design process, the placements of macros are considered. This crucial step determines the locations and orientations of macro cells within the chip's layout. By carefully arranging the macros, designers aim to achieve desired objectives such as optimizing performance, reducing power consumption, minimizing area utilization, and ensuring efficient connectivity. The floor planning process plays a vital role in shaping the overall physical layout of the System-on-a-Chip (SoC) and sets the foundation for subsequent design stages.
Global Optimization Assisted pLacement (GOAL)
GOAL delivers highly optimized macro placement solutions for the SoC design, with a dual focus on reducing routing wirelength and minimizing routing congestion to enhance overall performance. Traditionally, macro placement during floorplanning has relied on the experience and knowledge of backend engineers. However, as the number of instances in SoC design grows, this manual approach became relatively time-consuming, resy=ulting in the major factor for delay in time-to-market.
To overcome these challenges and to expedite time-to-market, one needs an efficient macro placement solution. GOAL was developed to address a very complex combinatorial optimization problem of macro placement. By utilizing the Conformational Space Annealing (CSA) global optimization technique, GOAL explores the vast solution space of macro placement where locations as well as orientations of macro cells are variables, and generates a collection of diverse and well-optimized macro placements that satisfy various design objectives and constraints.
Smart automation of the macro placement process can significantly accelerates floorplanning job and reduce the dependency on manual methods, hence enhancing time-to-market. This allows backend engineers to focus on other higher-level design decision making processes and ptimize other aspects of the physical design process.
With GOAL, design efficiency, accuracy, and time-to-market for SoC designs can be greatly improved. This enables designers to meet project timelines while delivering high-quality products.
GOAL – semiconductor design
GOAL delivers highly optimized macro placement solutions for the System-on-a-Chip (SoC) design, with a focus on reducing routing wirelength and minimizing routing congestion to enhance overall performance in a significantly reduced timeframe.
Learning is not required
Minimizing both wirelength and congestion
Simultaneous achievements of exceptional and diverse results